1. Field of the Invention
The present invention relates to a switching amplifier having a pulse-width modulating circuit.
2. Description of the Related Art
FIG. 5 is a circuit diagram illustrating a pulse-width modulating circuit proposed by the applicants of this invention. This circuit is not publicly known at the time of the application. The pulse-width modulating circuit charges/discharges capacitors C1 and C2 by means of collector electric currents I1 and I2 of transistors Q1 and Q2, so as to output pulses having two levels composed of a high level and a low level from inverters INV1 and INV2. The pulse-width modulating circuit inputs an audio signal in as an input signal, controls a distribution ratio between collector currents of the transistors Q1 and Q2 from a constant current, and controls charging time of the capacitors C1 and C2 so as to modulate pulse widths of output pulses. As a result, the pulse-width modulating circuit outputs PWM (pulse-width modulation) signals from the inverters INV1 and INV2.
The pulse-width modulating circuit alternately repeats a state that one of inputs of the inverters INV1 and INV2 is at a high level and the other input is at a low level, so as to be capable of outputting PWM signals. However, when both the capacitors C1 and C2 are charged and both the inputs of the inverters INV1 and INV2 are at the high level, the pulse-width modulating circuit cannot output the PWM signals. The details are described below.
FIG. 3 is a timing chart illustrating voltage waveforms at respective points of the pulse-width modulating circuit. Power supply voltages of the inverters INV1 and INV2 are logic power supply voltages Vdd (for example, 5 V) with respect to a reference potential V3. Threshold voltages Vth of the inverters INV1 and INV2 are about Vdd/2. At time t1 to t2, the electric current I1 flows into the capacitor C1 so as to charge the capacitor C1. When the capacitor C1 is charged, a voltage at point A gradually rises. At time t2, when the input (voltage at point A) of the inverter INV1 is the threshold voltage Vth or more of the inverter INV1, an output (voltage at point B) of the inverter INV1 is inverted from the high level to the low level. When the output from the inverter INV1 is at the low level, the capacitor C2 is discharged (the capacitor C2 is discharged when the voltage at point B becomes 5 V (t1 to t2) and electric charges of 5.6 V or more pass through a logic power supply via the diode D2), an input (voltage at point C) of the inverter INV2 connected to the output of the inverter INV1 via the capacitor C2 is at a low level, and an output of the inverter INV2 (voltage at point D) is inverted from a low level into a high level. When the output of the inverter INV2 is inverted into the high level, the input of the inverter INV1 (voltage at point A) is at the high level. Thereafter, the capacitor C2 is charged with the electric currents I2 so that a reverse operation to the above operation is performed (time t2 to t3).
A time required for the input of the inverter INV1 at the low level to reach the threshold voltage Vth due to the charging of the capacitor C1 is controlled by a magnitude of the electric currents I1. A time required for the input of the inverter INV2 at the low level to reach the threshold voltage Vth due to the charging of the capacitor C2 is controlled by a magnitude of the electric currents I2. The repetition of this operation causes the inverters INV1 and INV2 to alternately output a high-level or low-level pulse.
Although the input (voltage at point A) of the inverter INV1 is inverted from the low level into the high level at time t2, a voltage value at this time becomes a value obtained by adding a logic power supply voltage Vdd to the threshold voltage Vth (for example, 5+2.5=7.5 V). This voltage has the value viewed from the reference potential V3. Since the input (point A) of the inverter INV1 is discharged to a logic power supply voltage Vdd via a diode D1 during time t2 to t3, the voltage is stabilized at a value (for example, 5.6 V) obtained by adding a voltage between both ends (for example, 0.6 V) of the diode D1 to the logic power supply voltage Vdd. Although the voltage of the input (point A) of the inverter INV1 is inverted from the high level into the low level at time t3, it is not completely reduced to the reference potential V3 and is reduced to a value obtained such that the reference potential V3+ the voltage between both ends (for example, 0.6 V) of the diode D1.
When a switching amplifier to which the pulse-width modulating circuit is applied transitions from a power-on state into a power-off state, both the inputs of the inverters INV1 and INV2 are brought into the high level, and thus PWM signals cannot be output. That is to say, in a transient state of the transition into the power-off state, as a first power supply voltage V1 reduces, the logic power supply voltage Vdd generated from the first power supply voltage V1 reduces. When the logic power supply voltage Vdd with respect to the reference potential V3 reduces to a value less than a voltage (for example, 1.2 V) twice as high as the voltage between both ends of the diodes D1 and D2, the threshold voltages Vth of the inverters INV1 and INV2 are less than the voltage between both ends (for example, 0.6 V) of the diodes D1 and D2. Therefore, when the electric currents I1 and I2 are supplied to the capacitor C1 and C2, respectively and the charging and discharging of the capacitors C1 and C2 are repeated in this state, in FIGS. 3A and 3C, when the inputs of the inverters INV1 and INV2 are inverted from the high level into the low level, lowest voltages of the input of the inverters INV1 and INV2 cannot be the threshold voltages or less of the inverters INV1 and INV2. This is because although the voltages of the inputs of the inverters INV1 and INV2 reduce to only the reference potential V3+ the voltage between the both ends of the diodes D1 and D2 (for example, 0.6 V), the threshold voltages Vth of the inverters INV1 and INV2 reduce to not more than the value obtained by the reference potential V3+ the voltage between the both ends of the diodes D1 and D2. As a result, a state where both the inputs of the inverters INV1 and INV2 are at the high level is generated, and thus the pulse-width modulating circuit cannot output PWM signals.
When the switching amplifier is powered on after powered off and then sufficient time passes, charging voltages of the capacitors C1 and C2 are discharged or the operations of the inverters INV1 and INV2 stop. In this state, since both of them do not output low-level voltages, the pulse-width modulating circuit can normally start its operation. However, in a state that the first power supply voltage V1 and the reference potential V3 are not yet 0 V, the inverters INV1 and INV2 still continue the operations, both the inputs are at the high level, and both the outputs are low level, when the power is again turned on, the pulse-width modulating circuit cannot start the operation and stops.